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CXA2108AQ constant-current driver for full color led display description the CXA2108AQ is a 1,024-gradation led driver which is ideal for full color led displays. this ic has 24 outputs and a maximum output current of 70ma. time division allows driving of either two or six leds per output by connecting an external fet or other switch. the luminance (pwm) and drive current for each led are set using the internal ram. the led type is common anode. features 24 outputs: 10-bit (1,024-gradation) pwm current outputs maximum output current: 70ma led type: common anode 4-bit brightness function capable of switching the basic pwm pulse width in 16 steps time division allows driving of up to six leds with a single output, making it possible to configure a high definition display with few driver ics. coarse adj. (2 bits) and fine adj. (8 bits) output current adjustment for each led makes it possible to drive r, g and b using the same output from the same ic. in addition, the characteristics variance of each led can also be corrected. all luminance (pwm) data and drive current data are set by writing to the internal ram. pwm emitting can be performed up to 15 times per frame to realize a screen with little flicker. two built-in pwm data ram make it possible to set the next luminance data even during pwm operation. abnormal internal temperature detection circuit single 5v power supply current output with protection diode (diode cathode voltage: vpd can be supplied independently of the 5v power supply.) surface mounting package (80-pin qfp) applications led display panels structure bi-cmos silicon monolithic ic absolute maximum ratings (ta = 25?) supply voltage av cc , dv cc ?.3 to +6.0 v vpd ?.3 to +10.5 v digital input voltage v i _d ?.3 to dv cc + 0.3 v digital output current io_d ?.0 to +5.0 ma driver output voltage v_dvr 0 to vpd + 0.3 v driver output current i_dvr ? to +80 ma operating temperature * 1 topr ?0 to +80 ? storage temperature tstg ?5 to +150 ? allowable power dissipation * 1 (ta = 65? or less) p d 1.5 w recommended operating range supply voltage av cc , dv cc 4.75 to 5.25 v vpd av cc to 10 v driver output compliance voltage vcmp 1.0 to vpd + 0.3 v (i_dvr = 0 to 70ma) operating temperature (ambient temperature) * 1 ta ?0 to +65 ? operating temperature (case temperature) * 1 tc ?0 to +110 ? * 1 when mounted on a printed circuit board ?1 e99160-ps sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 80 pin qfp (plastic)
? 2 CXA2108AQ block diagram p w m d a t a r a m ( b ) ( 6 w o r d 2 4 c h 1 0 b i t ) p w m d a t a r a m ( a ) ( 6 w o r d 2 4 c h 1 0 b i t ) d a t a r e a d c o u n t e r d r i v e c u r r e n t d a t a r a m ( 6 w o r d 2 4 c h 1 0 b i t ) 1 0 b i t 2 4 s h i f t r e g . & l a t c h p w m d a t a 1 0 b i t 2 4 s h i f t r e g . & l a t c h 8 b i t d a c w i t h 2 b i t c o a r s e a d j . ( 2 4 ) 2 4 d l d i c l k i o u t 2 3 a 0 t o 9 1 0 m o d e r d y d 0 t o 9 x t a o r e x t x r / w x r d x w r 1 0 1 0 d a t a 1 0 2 4 r e x t 2 4 1 0 2 4 2 4 p w m o u t p w m c o u n t e r 1 0 d a t a 4 1 0 c o u n t e r o u t d a t a c o m p a r a t o r b a n d g a p r e f . 9 b r t r _ a d r r _ c l k i o u t 0 x b x g x r x u p r d l d o d r i v e c u r r e n t d a t a
? 3 CXA2108AQ pin configuration (top view) 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 a 0 a 1 a 2 a 3 a 4 a 5 a 6 i o u t 5 i o u t 4 i o u t 3 i o u t 2 i g n d i o u t 1 i o u t 0 a v c c a g n d r e x t n c n c x t a o x r s t x r / w x r d x w r x c s d l d i a 9 4 1 4 2 4 3 4 4 a 8 d v c c d g n d a 7 i o u t 1 8 i o u t 1 9 i o u t 2 0 i o u t 2 1 i g n d i o u t 2 2 i o u t 2 3 a v c c a g n d v p d m o d e d g n d r d y d l d o 2 1 2 2 2 3 2 4 c l k d g n d d v c c d 0 w a l l x u p r t e s t _ o x b x r x g i o u t 1 7 i g n d i o u t 1 6 i o u t 1 5 i o u t 1 4 i g n d i o u t 1 3 i o u t 1 2 i o u t 1 1 i o u t 1 0 i g n d i o u t 9 i o u t 8 i o u t 7 i g n d i o u t 6
? 4 CXA2108AQ pin no. symbol equivalent circuit description reference voltage level i/o pin description analog gnd. 9, 56 agnd gnd analog power supply. 8, 57 av cc 5v (typ.) digital gnd. 12, 22, 42 dgnd gnd digital power supply. 23, 43 dv cc 5v (typ.) gnd for driver output. 5, 60, 66, 70, 75, 79 ignd gnd open. this pin is not connected with the internal circuits. 53, 54 nc d g n d d v c c 4 0 3 7 3 4 2 1 4 1 3 8 3 5 5 1 4 4 3 9 3 6 1 1 4 5 clock input. driver operation is synchronized with this clock. reset input. the ic is initialized by inputting low level. however, the memory is not initialized. input high level during normal operation. output mode switching. upper/lower mode for low level input. upper/lower/rgb mode for high level input. (see the description of operation.) address input. these pins are used to input the internal ram (luminance data, brightness data and drive current data ram) address. ram selection. the luminance data ram is selected when this pin is low, and the drive current data ram when high. 21 clk cmos i 51 xrst cmos i 11 mode cmos i 34 to 41, 44 a0 to 8 cmos i 45 a9 cmos i d g n d d v c c 3 0 2 7 2 4 3 1 2 8 2 5 3 2 2 9 2 6 3 3 d g n d d v c c data i/o. these pins are used to input and output data to and from the internal ram (luminance data, brightness data and drive current data ram). see table 1. read/write switching condition correspondence table for the data i/o switching conditions. 24 to 33 d0 to 9 cmos i/o
? 5 CXA2108AQ d g n d d v c c 4 9 4 6 5 0 4 7 4 8 internal ram chip select. internal ram access is enabled by inputting low level. (see table 1. read/write switching condition correspondence table.) internal ram read/write select. write mode is selected for high level, and read mode for low level. see table 1. read/write switching condition correspondence table for the actual read/write switching signal input conditions. write clock input. this pin is used to input the clock for writing the luminance, brightness and drive current data. it is not synchronized with clk. read clock input. this pin is used to input the clock for externally reading the luminance, brightness and drive current data. it is not synchronized with clk. trigger signal input for luminance data ram (a)/(b) switching and pwm output start. (see the timing charts.) 47 xcs cmos i 50 xr/w cmos i 48 xwr cmos i 49 xrd cmos i 46 dldi cmos i pin no. symbol equivalent circuit description reference voltage level i/o voltage supply terminal for cathode of positive protection diode which connected to drivers (iouto to iout23) and rext (55pin). normally,connect to led dc supply. however ,when the led dc supply voltage exceeds 10v,vpd must be set 10v or less. 10 vpd 5v (typ.)
? 6 CXA2108AQ d g n d d v c c 1 9 1 6 1 3 2 0 1 7 1 4 5 2 1 8 1 5 ready signal output. this indicates the drive current data ram access enabled period. access is enabled while high level is output. (see the timing charts.) dldi signal output. this outputs the dldi signal synchronized with clk. write all signal output. one pulse (= high level signal with a width of 1 clock) is output synchronized with the rising edge of the next clk after the final address * 1 of the currently selected mode is input. note that both the final address must be input and the xcs and xwr input levels must be low at the rising edge of this clk. (see the timing charts for details.) * 1 02fh (upper/lower mode) 08fh (upper/lower/rgb mode) upper signal output. this is used as the led switching signal. (see the timing charts and application circuits for details.) test signal output. this pin is unrelated to the functions of this ic. do not connect anything; leave this pin open. blue signal output. this is used as the led switching signal. (see the timing charts and application circuits for details.) red signal output. this is used as the led switching signal. (see the timing charts and application circuits for details.) green signal output. this is used as the led switching signal. (see the timing charts and application circuits for details.) thermal alarm out signal output. this pin normally outputs high level, but it outputs low level when the internal temperature rises to an abnormally high level. 13 rdy cmos o 14 dldo cmos o 15 wall cmos o 16 xupr cmos o 17 test_o cmos o 18 xb cmos o 19 xr cmos o 20 xg cmos o 52 xtao cmos o pin no. symbol equivalent circuit description reference voltage level i/o
? 7 CXA2108AQ i g n d v p d 1 2 3 4 6 7 5 8 5 9 6 1 6 2 6 3 6 4 6 7 6 8 6 9 7 1 7 2 7 3 7 4 7 6 7 7 7 8 8 0 6 5 drivers. these pins drive the led. 1 to 4, 6, 7, 58, 59, 61 to 65, 67 to 69, 71 to 74, 76 to 78, 80 iout0 to 23 o xcs [ i ] l h xr/w [ i ] l h l h a9 [ i ] l h l h l h l h luminance write disable disable enable disable disable disable disable disable enable disable disable disable disable disable disable disable disable disable disable enable disable disable disable disable disable enable disable disable disable disable disable disable read drive current d0 to 9 [i/o] output output input input hi-z hi-z hi-z hi-z write read table 1. read/write switching condition correspondence table a g n d v p d 5 5 drive current setting. connect a resistor between this pin and gnd. the drive current is proportional to the current flowing to this resistor. (see table 2. drive current setting and power consumption.) 55 rext o pin no. symbol equivalent circuit description reference voltage level i/o
? 8 CXA2108AQ rext [k ] d9 d8 io (ffh) [ma] istb [ma] pstb [w] po (max) [w] * 1 absolute maximum rating exceeded. table 2. drive current setting and power consumption (when d0 to d7 = ffh) rext : external resistor that sets the dac reference current (iref) d9, d8 : data that sets the maximum drive current (io (ffh)) iref : dac reference current iref [ma] = 1.3 [v]/rext [k ]/24 io (ffh) : maximum drive current that can be set by d0 to d7 io (ffh) [ma] = iref (2 d9 + d8 + 1) 800 istb : standby current (internal current consumption excluding the driver block) istb [ma] = 3.06 + 24 iref (16/3 + 24.25 (2 d9 + d8 + 1)) pstb : standby power (internal power consumption excluding the driver block, vcc = 5 v) pstb [w] = 5 [v] istb [ma]/1000 po (max) : maximum power that can be consumed by the driver block po (max) [w] = 1.5 [w] ?pstb [w] note) istb, pstb and po (max) are the values when d0 to d7 = 11111111 (ffh). in addition, these values assume the case where all channels are set to the same drive current. 2.0 2.0 2.0 2.0 2.5 2.5 2.5 2.5 3.0 3.0 3.0 3.0 3.5 3.5 3.5 3.5 4.0 4.0 4.0 4.0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 21.7 43.3 65.0 86.7 * 1 17.3 34.7 52.0 69.3 14.4 28.9 43.3 57.8 12.4 24.8 37.1 49.5 10.8 21.7 32.5 43.3 22.3 38.1 53.8 69.6 18.4 31.1 43.7 56.3 15.9 26.4 36.9 47.4 14.0 23.1 32.1 41.1 12.7 20.6 28.4 36.3 0.111 0.190 0.269 0.348 0.092 0.155 0.218 0.281 0.079 0.132 0.184 0.237 0.070 0.115 0.160 0.205 0.063 0.103 0.142 0.182 1.39 1.31 1.23 1.15 1.41 1.34 1.28 1.22 1.42 1.37 1.32 1.26 1.43 1.38 1.34 1.29 1.44 1.40 1.36 1.32
? 9 CXA2108AQ electrical characteristics (av cc , dv cc = +5v, vpd = +10v, agnd, dgnd, ignd = 0v) pwm output resolution bit 10 drive current setting resolution coarse adj. bit 2 fine adj. bit 8 dle 0.8 io (ffh) = 60ma (d0 [lsb] to d7 [msb] = ffh) dc characteristics differential linearity error lsb f clk 15 pwm reference clock frequency mhz item symbol conditions min. typ. max. unit driver block v rext 1365 1235 rext = 2k rext pin voltage mv 1300 ? v rext 20 0 v rext (@av cc = 5.25v) ?v rext (@av cc = 4.75v) rext pin voltage supply voltage dependency mv i cc 30 20 rext = 2k , d8 = d9 = 0 note) excluding the driver block standby supply current ma i out 70 output current ma output compliance voltage logic block digital input current (i, i/o) vcmp vpd + 0.3 1 io = 0 to 70ma v (h) i ih 5 ? v in = 5v a (l) i il 5 ? v in = 0v a digital input voltage (i, i/o) (h) v ih dv cc + 0.3 0.7dv cc v (l) v i l 0.3dv cc ?.3 v digital output voltage (o) (h) v oh 4 dv cc = 5v, i oh = ?ma v (l) v ol 0.4 dv cc = 5v, i ol = 4ma v digital output voltage (i/o) (h) v ozh 3.7 dv cc = 5v, i oh = ?ma v (l) v ozl 0.4 dv cc = 5v, i ol = 4ma v ram write mode write cycle t wr 133.3 ns write pulse width t cwr 55 ns setup time t swr 10 ns hold time t hwr 10 ns ram read mode read cycle t rd 133.3 ns read pulse width t crd 55 ns setup time t srd 10 ns hold time t hrd 10 ns output delay time t pdd 100 output load 50pf or less ns
? 10 CXA2108AQ timing charts (ram) (1) write mode (xr/w = h) x r d t r d t c r d t s r d a 0 t o 9 d 0 t o 9 t p d d t h r d note) the address is not latched internally, so do not change the address while xwr is low. (1) read mode (xr/w = l) x w r t w r t c w r t s w r a 0 t o 9 d 0 t o 9 t h w r note) the address is not latched internally, so do not change the address while xrd is low.
? 11 CXA2108AQ electrical characteristics measurement circuit dc characteristics measurement circuit a x r s t a v c c d v c c 5 v 1 v l o g i c t e s t e r c x a 2 1 0 8 a q m o d e x r / w i o u t 0 t o 2 3 x r d x w r d l d i a 0 t o 9 d 0 t o 9 1 0 0 v 5 v 1 5 m h z x c s c l k 2 k w a g n d d g n d i g n d r e x t 1 0 v p d 1 0 v
? 12 CXA2108AQ description of operation 1. description the CXA2108AQ is an led driver for full color led displays. the rgb luminance which becomes the video data is controlled by pulse width modulation (pwm), and the luminance variance of each led is corrected by the drive current. the basic pwm clock width can be set in 16 steps from 1 to 16 by the brightness data, making it possible to adjust the brightness of the entire screen. there are 24 driver outputs, and time division allows driving of either two or six leds per output by adding an external fet or other switch. the luminance (pulse width), drive current and brightness are set by writing data to the internal memory according to the memory map. the luminance and drive current can be set independently for each led. 2. relationship between the luminance data (pwm data: dv), brightness data (db) and the led emitting duty the CXA2108AQ adjusts the led luminance which becomes the video data by changing the led emitting time duty through pwm of the luminance data. the luminance consists of luminance data and brightness data. the luminance data (dv) has an accuracy of 10 bits (= 1,024 steps: 0 to 1,023) and can be set independently for each led. the brightness data (db) controls the basic pwm clock width with 4 bits (= 16 steps: 1 to 16 ), and is common data for all outputs. the brightness data is normally used when adjusting the brightness of the entire screen. labeling the led emitting cycle as ts and the clk cycle as t clk , this relationship is given by the following formula. ts = 1,024 16 t clk the led emitting time tv within this ts time is: tv = dv db t clk therefore, the emitting duty is: tv/ts 100 = (dv db)/(1,024 16) 100 [%] the drive current waveform and the relationship between the luminance data, brightness data and the emitting duty are shown below. c u r r e n t d r i v e c u r r e n t i o u t 0 t v = d v d b t c l k t s = 1 , 0 2 4 1 6 t c l k t s t i m e fig. 1. drive current waveform
? 13 CXA2108AQ 3. drive current data (dd) even when driving leds of the same color with the same current value, individual differences in characteristics result in an uneven emitting intensity. in addition, the required current value also differs according to the emitting color (rgb). that is to say, the necessary current differs for each led. this drive current iout corresponds to the amplitude of the iout output pwm waveform as shown in fig. 1. the CXA2108AQ can set this current independently for each led using coarse adj. (2 bits: d8, d9) and fine adj. (8 bits: d0 to d7). the maximum values of the drive current (io (ffh): iout @ d0 to d7 = ffh) are varied in 4 levels by coarse adj. (2 bits: d8, d9). the minimum drive current (io (00h): iout @ d0 to d7 = 00h) is approximately 0ma,regardless of the coarse adj. range. the range from the minimum to the maximum drive current can be set at an accuracy of 8 bits (d0 to d7 = 256 steps). note that this drive current is generated using the iref described in 6. as the reference. the relationship between the fine adj. (8 bits: d0 to d7) data and the drive current, and the drive current data (d0 to d9) to drive current correspondence table are shown below. drive current d9 d8 0 0 d9 d8 0 1 d9 d8 1 0 d9 d8 1 1 drive current data (dd) d7 to 0 d7 d0 00000000 (00h) : 10000000 (80h) : 11111111 (ffh) 0 : 400 iref : 800 iref 0 : 800 iref : 1600 iref 0 : 1200 iref : 2400 iref 0 : 1600 iref : 3200 iref minimum drive current io (00h) maximum drive current io (ffh) table 4. drive current data (d0 to d9) to drive current correspondence table nv * 1 and emitting duty nv brightness (d3 to 0) = 0000 emitting duty [%] luminance data (dv) d9 to 0 d9 d0 0000000000 0000000001 0000000010 : 1000000000 : 1111111111 0 1 2 : 512 : 1023 0 0.006 0.012 : 3.125 : 6.244 : : nv brightness (d3 to 0) = 0111 emitting duty [%] 0 8 16 : 4096 : 8184 0 0.049 0.098 : 25.00 : 49.95 nv brightness (d3 to 0) = 1111 emitting duty [%] 0 16 32 : 8192 : 16368 0 0.098 0.195 : 50.00 : 99.90 table 3. relationship between luminance data, brightness data and emitting duty * 1 nv = tv/t clk = dv db d r i v e c u r r e n t ( m a x i m u m d r i v e c u r r e n t ) f i n e a d j . ( 8 b i t s : d 0 t o d 7 ) d a t a i o ( f f h ) i o ( 0 0 h ) 0 0 1 h 1 l s b = i o ( f f h ) / 2 5 5 ( 2 5 6 s t e p s ) 0 0 h f e h f f h ( m i n i m u m d r i v e c u r r e n t ) fig. 2. relationship between fine adj. (8 bits: d0 to d7) data and drive current
? 14 CXA2108AQ 4. operating modes (upper/lower, upper/lower/rgb) the CXA2108AQ has the following two operation modes which are set by the mode pin. 4-1. upper/lower mode (mode = low) in this mode, two leds are driven by time division for each iout output. first, pwm waveform output starts triggered by the dldi input signal. in this mode, two kinds of luminance data are output by time division for each output. labeling these data as u and l, the driver outputs the data in the order of u ? l ? u ? l ? u ? and so on. the xupr pin output voltage switches in sync with the led emitting cycle ts in the order of l ? h ? l ? and so on, so this can be used as the fet or other switch signal for switching the led. (see fig. 6. timing chart 2-1 and fig. 11. application circuit (1) for details.) new pwm data is output when the next dldi signal is input. 4-2. upper/lower/rgb mode (mode = high) in this mode, six leds can be driven by time division for each iout output. pwm waveform output starts triggered by the dldi input signal. in this mode, six kinds of luminance data are output by time division for each output. labeling these data as ub, ur, ug, lb, lr and lg, the driver switches the output in the order of ub ? ur ? ug ? lb ? lr ? lg ? ub ? and so on. like upper/lower mode, the xupr and also the xb, xr and xg output voltages switch in sync with ts, so these can be used as the fet or other switch signals for switching the leds. the output voltages at this time are: xupr = low for u * , xupr = high for l * , xb = low (xr = xg = high) for * b, xr = low (xb = xg = high) for * r, and xg = low (xb = xr = high) for * g. (see fig. 7. timing chart 2-2 and fig. 12. application circuit (2) for details.) new pwm data is output when the next dldi signal is input. 5. luminance data memory and dldi signal the CXA2108AQ uses two sets of 6-word 24-channel 10-bit ram (ram (a), ram (b)) as luminance data memories, and switches these memories. while the data in one memory is being loaded internally and pwm output is being performed, the next luminance data can be written to the other memory from an external source. memory switching is performed by inputting a trigger signal to the dldi pin. the read/write enabled memory alternates from a ? b ? a ? and so on, and the memory used for pwm output alternates from b ? a ? b ? and so on each time the signal is input to dldi. the dldi signal switches the memory, and at the same time functions as the pwm output start trigger pulse. see the timing charts for details. 6. reference current (iref) the drive current is generated using the current flowing to an external resistor as the reference. this resistor rext is connected between the rext pin and gnd. the rext pin voltage is designed to be unaffected by supply voltage, temperature or other fluctuations, and is always a constant voltage (approximately 1.3v). therefore, a constant current can be realized by using a resistor that does not have temperature characteristics. the current obtained by dividing this current value by the number of iout outputs (24) is defined as iref. iref = (1.3/rext)/24 the maximum drive current value can be changed by varying the resistance value. see table 2. drive current setting and power consumption for details.
? 15 CXA2108AQ 7. data setting the above mentioned luminance data dv, brightness data db and drive current data dd are set using address input pins a0 to a9 and data i/o pins d0 to d9. see the timing charts for the memory read/write enabled period, and table 1. read/write switching condition correspondence table for the pin setting conditions. the address, data, xwr and xrd setup, hold and other timings should be as stated in the electrical characteristics. see tables 5. and 6. led driver memory map with respect to the memory address of each iout output pin (iout0 to iout23). the relationship between the data and the memory address is as follows. b r i g h t n e s s d a t a 0 1 0 0 1 0 1 0 0 0 l g l r l b u g u r u b u p p e r / l o w e r / r g b n o t e ) x : d o n ' t c a r e c a n ' t u s e b r i g h t n e s s d a t a l i o u t 0 i o u t 1 i o u t 2 i o u t 3 i o u t 4 i o u t 2 3 a + 2 3 a i o u t 2 1 i o u t 2 2 u u p p e r / l o w e r c a n ' t u s e 0 1 0 0 1 0 0 x x x 0 1 0 0 0 1 1 1 1 1 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 m o d e d o n ' t u s e d o n ' t u s e fig. 3. relationship between memory address and data (luminance data dv, brightness data db) a9 to a0 msb lsb a9 a0
? 16 CXA2108AQ l g l r l b u g u r u b u p p e r / l o w e r / r g b c a n ' t u s e l i o u t 0 i o u t 1 i o u t 2 i o u t 3 i o u t 4 i o u t 2 3 a + 2 3 a i o u t 2 1 i o u t 2 2 u u p p e r / l o w e r c a n ' t u s e 1 0 1 0 0 1 0 0 0 0 1 0 1 0 0 0 1 1 1 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 1 0 1 1 1 1 0 0 1 1 0 0 0 0 0 1 0 0 1 0 1 1 1 1 1 1 0 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 m o d e fig. 4. relationship between memory address and data (drive current data dd) a9 to a0 msb lsb a9 a0
? 17 CXA2108AQ iout0 iout1 iout2 iout3 iout4 iout5 iout6 iout7 iout8 iout9 iout10 iout11 iout12 iout13 iout14 iout15 iout16 iout17 iout18 iout19 iout20 iout21 iout22 iout23 iout0 iout1 iout2 iout3 iout4 iout5 iout6 iout7 iout8 iout9 iout10 iout11 iout12 iout13 iout14 iout15 iout16 iout17 iout18 iout19 iout20 iout21 iout22 iout23 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 a9 to a3 upper lower a2 to a0 000 001 010 011 100 101 110 111 iout0 iout1 iout2 iout3 iout4 iout5 iout6 iout7 iout8 iout9 iout10 iout11 iout12 iout13 iout14 iout15 iout16 iout17 iout18 iout19 iout20 iout21 iout22 iout23 iout0 iout1 iout2 iout3 iout4 iout5 iout6 iout7 iout8 iout9 iout10 iout11 iout12 iout13 iout14 iout15 iout16 iout17 iout18 iout19 iout20 iout21 iout22 iout23 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 1010000 1010001 upper lower a2 to a0 000 001 010 011 100 101 110 111 luminance data drive current data brightness data: a9 to a3 = 0100100b (24h) a2 to a0 = don't care table 5. led driver memory map (upper/lower mode) l u l u
? 18 CXA2108AQ iout0 iout1 iout2 iout3 iout4 iout5 iout6 iout7 iout8 iout9 iout10 iout11 iout12 iout13 iout14 iout15 iout16 iout17 iout18 iout19 iout20 iout21 iout22 iout23 iout0 iout1 iout2 iout3 iout4 iout5 iout6 iout7 iout8 iout9 iout10 iout11 iout12 iout13 iout14 iout15 iout16 iout17 iout18 iout19 iout20 iout21 iout22 iout23 iout0 iout1 iout2 iout3 iout4 iout5 iout6 iout7 iout8 iout9 iout10 iout11 iout12 iout13 iout14 iout15 iout16 iout17 iout18 iout19 iout20 iout21 iout22 iout23 iout0 iout1 iout2 iout3 iout4 iout5 iout6 iout7 iout8 iout9 iout10 iout11 iout12 iout13 iout14 iout15 iout16 iout17 iout18 iout19 iout20 iout21 iout22 iout23 iout0 iout1 iout2 iout3 iout4 iout5 iout6 iout7 iout8 iout9 iout10 iout11 iout12 iout13 iout14 iout15 iout16 iout17 iout18 iout19 iout20 iout21 iout22 iout23 iout0 iout1 iout2 iout3 iout4 iout5 iout6 iout7 iout8 iout9 iout10 iout11 iout12 iout13 iout14 iout15 iout16 iout17 iout18 iout19 iout20 iout21 iout22 iout23 0000000 0000001 0000010 0000011 0000100 0000101 0000110 0000111 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 a9 to a3 b r upper g b r lower g a2 to a0 000 001 010 011 100 101 110 111 iout0 iout1 iout2 iout3 iout4 iout5 iout6 iout7 iout8 iout9 iout10 iout11 iout12 iout13 iout14 iout15 iout16 iout17 iout18 iout19 iout20 iout21 iout22 iout23 iout0 iout1 iout2 iout3 iout4 iout5 iout6 iout7 iout8 iout9 iout10 iout11 iout12 iout13 iout14 iout15 iout16 iout17 iout18 iout19 iout20 iout21 iout22 iout23 iout0 iout1 iout2 iout3 iout4 iout5 iout6 iout7 iout8 iout9 iout10 iout11 iout12 iout13 iout14 iout15 iout16 iout17 iout18 iout19 iout20 iout21 iout22 iout23 iout0 iout1 iout2 iout3 iout4 iout5 iout6 iout7 iout8 iout9 iout10 iout11 iout12 iout13 iout14 iout15 iout16 iout17 iout18 iout19 iout20 iout21 iout22 iout23 iout0 iout1 iout2 iout3 iout4 iout5 iout6 iout7 iout8 iout9 iout10 iout11 iout12 iout13 iout14 iout15 iout16 iout17 iout18 iout19 iout20 iout21 iout22 iout23 iout0 iout1 iout2 iout3 iout4 iout5 iout6 iout7 iout8 iout9 iout10 iout11 iout12 iout13 iout14 iout15 iout16 iout17 iout18 iout19 iout20 iout21 iout22 iout23 1000000 1000001 1000010 1000011 1000100 1000101 1000110 1000111 1001000 1001001 1001010 1001011 1001100 1001101 1001110 1001111 1010000 1010001 b r upper g b lower r g a2 to a0 000 001 010 011 100 101 110 111 luminance data drive current data brightness data: a9 to a3 = 0100100b (24h) a2 to a0 = don't care table 6. led driver memory map (upper/lower/rgb mode) l g l r l b u g u r u b u g u r u b l g l r l b
? 19 CXA2108AQ u l u l u l u r a m ( a ) r / w d i s a b l e ( a c c e s s i n g i n t e r n a l l y ) r a m ( a ) r a m ( b ) d l d i i o u t o u t p u t d a t a p a r t i a l e n l a r g e m e n t d i a g r a m ( f i g . 6 . t i m i n g c h a r t 2 - 1 ) r / w e n a b l e r / w d i s a b l e r / w e n a b l e r / w e n a b l e r / w e n a b l e l u l u u l r / w d i s a b l e ( a c c e s s i n g i n t e r n a l l y ) u l u l u l u l u u l u l u l u r a m ( b ) r a m ( a ) u b u r u g l b l r l g u b r a m ( a ) r / w d i s a b l e ( a c c e s s i n g i n t e r n a l l y ) r a m ( a ) r a m ( b ) d l d i i o u t o u t p u t d a t a p a r t i a l e n l a r g e m e n t d i a g r a m ( f i g . 7 . t i m i n g c h a r t 2 - 2 ) r / w e n a b l e r / w d i s a b l e r / w e n a b l e r / w e n a b l e r / w e n a b l e u r u g l b l r u b u r r / w d i s a b l e ( a c c e s s i n g i n t e r n a l l y ) u g l b l r l g u b u r u g l b l r u b u r u g l b l r l g u b r a m ( b ) r a m ( a ) n o t e ) u , l a n d o t h e r s y m b o l s c o r r e s p o n d t o t a b l e s 5 . a n d 6 . l e d d r i v e r m e m o r y m a p . fig. 5. timing chart 1. relationship between pwm waveform output and luminance ram (a)/(b) with respect to dldi input pulse case 1: upper/lower mode case 2: upper/lower/rgb mode
? 20 CXA2108AQ d l d i d l d o r d y i o u t x u p r p a r t i a l e n l a r g e m e n t d i a g r a m ( f i g . 8 . t i m i n g c h a r t 3 - 1 ) n o t e ) u , l a n d o t h e r s y m b o l s c o r r e s p o n d t o t a b l e s 5 . l e d d r i v e r m e m o r y m a p . 1 c l k 1 0 2 4 1 6 c l k = 1 c y c l e u e m i t t i n g s t a r t e m i t t i n g e n d l u l u l u fig. 6. timing chart 2-1. dldi input to iout output (upper/lower mode)
? 21 CXA2108AQ fig. 7. timing chart 2-2. dldi input to iout output (upper/lower/rgb mode) d l d i d l d o r d y i o u t x u p r p a r t i a l e n l a r g e m e n t d i a g r a m ( f i g . 9 . t i m i n g c h a r t 3 - 2 ) n o t e ) u b , l g a n d o t h e r s y m b o l s c o r r e s p o n d t o t a b l e s 6 . l e d d r i v e r m e m o r y m a p . 1 c l k 1 0 2 4 1 6 c l k = 1 c y c l e x b x r x g u b e m i t t i n g s t a r t e m i t t i n g e n d u r u g l b l r l g u b
? 22 CXA2108AQ 4 8 c l k 9 c l k 8 c l k 4 8 c l k x u p r r d y d l d o d l d i c l k n v c l k e m i t t i n g s t a r t e m i t t i n g s t a r t l u m i n a n c e d a t a r a m ( a ) e = r / w e n a b l e d = r / w d i s a b l e i o u t l u m i n a n c e d a t a r a m ( b ) d r i v e r c u r r e n t r a m e m i t t i n g e n d * n v = d v d b ( d v : l u m i n a n c e d a t a , d b : b r i g h t n e s s d a t a ) e d d e e d d e e 1 0 2 4 1 6 c l k = 1 c y c l e fig. 8. timing chart 3-1. dldi input to iout output (1 cycle) example (upper/lower mode)
? 23 CXA2108AQ fig. 9. timing chart 3-2. dldi input to iout output (1 cycle) example (upper/lower/rgb mode) 4 8 c l k 9 c l k 8 c l k 4 8 c l k x u p r r d y d l d o d l d i c l k n v c l k e m i t t i n g s t a r t e m i t t i n g s t a r t l u m i n a n c e d a t a r a m ( a ) e = r / w e n a b l e d = r / w d i s a b l e i o u t x g x r x b l u m i n a n c e d a t a r a m ( b ) d r i v e r c u r r e n t r a m e m i t t i n g e n d * n v = d v d b ( d v : l u m i n a n c e d a t a , d b : b r i g h t n e s s d a t a ) e d d e e d d e e 1 0 2 4 1 6 c l k = 1 c y c l e
? 24 CXA2108AQ 1 c l k = 1 5 m h z ( m a x ) 1 2 8 c l k 4 8 c l k 9 c l k 8 c l k n v c l k e m i t t i n g s t a r t l u m i n a n c e d a t a w r i t e l u m i n a n c e d a t a r a m ( a ) i o u t e = r / w e n a b l e d = r / w d i s a b l e x u p r r d y w a l l d l d o d l d i d 0 t o 9 a 0 t o 9 x r / w x w r x r s t c l k l u m i n a n c e d a t a r a m ( b ) d r i v e r c u r r e n t r a m b r i g h t n e s s d a t a w r i t e e m i t t i n g e n d 1 c l k = 7 . 5 m h z ( m a x ) 2 0 1 2 0 2 2 2 f 1 2 0 0 0 0 0 0 1 0 0 2 d d 1 d d 2 d d 2 f d b d v 0 d v 1 d v 2 d r i v e c u r r e n t d a t a w r i t e * n v = d v d b ( d v : l u m i n a n c e d a t a , d b : b r i g h t n e s s d a t a ) * d d : d r i v e c u r r e n t d a t a i c i n i t i a l i z a t i o n d e d e d d d e e 0 2 f d v 2 f d d 0 2 0 0 fig. 10. timing chart 4. xrst input to iout output example (upper/lower mode)
? 25 CXA2108AQ 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 i o u t 5 i o u t 4 i o u t 3 i o u t 2 i o u t 1 i o u t 0 a v c c a g n d b u s c l k ( 7 . 5 m h z ) r e x t r e a d / w r i t e c o n t r o l s i g n a l a d d r e s s : a 0 t o a 9 f r o m a d d r e s s b u s 2 k w x r / w x r d x w r 4 1 4 2 4 3 4 4 i o u t 1 8 i o u t 1 9 i o u t 2 0 i o u t 2 1 i o u t 2 2 i o u t 2 3 m o d e 2 1 2 2 2 3 2 4 1 5 m h z c l k x u p r i o u t 1 7 i o u t 1 6 i o u t 1 5 i o u t 1 4 i o u t 1 3 i o u t 1 2 i o u t 1 1 i o u t 1 0 i o u t 9 i o u t 8 i o u t 7 i o u t 6 a g n d i g n d i g n d i g n d i g n d i g n d d v c c d g n d d a t a : d 0 t o d 9 f r o m d a t a b u s d v c c d g n d i g n d a g n d d g n d d g n d a v c c v p d a d d r e s s b u s b u s c l k d a t a b u s 7 . 5 m h z 5 v 0 v 5 v 0 v 5 v 0 v v g , v r , v b : l e d d c s u p p l y v g = 5 . 5 v v r = 4 . 0 v v b = 5 . 5 v g g g g r e e n b b f r o m x u p r f r o m i o u t 2 3 f r o m i o u t 3 f r o m i o u t 2 f r o m i o u t 1 f r o m i o u t 0 r r e d b b u l e application circuit upper/lower mode fig. 11. application circuit (1) application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 26 CXA2108AQ 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 i o u t 5 i o u t 4 i o u t 3 i o u t 2 i o u t 1 i o u t 0 a v c c a g n d b u s c l k ( 7 . 5 m h z ) r e x t r e a d / w r i t e c o n t r o l s i g n a l a d d r e s s : a 0 t o a 9 f r o m a d d r e s s b u s 2 k w x r / w x r d x w r 4 1 4 2 4 3 4 4 i o u t 1 8 i o u t 1 9 i o u t 2 0 i o u t 2 1 i o u t 2 2 i o u t 2 3 m o d e 2 1 2 2 2 3 2 4 1 5 m h z c l k x u p r x b x r x g i o u t 1 7 i o u t 1 6 i o u t 1 5 i o u t 1 4 i o u t 1 3 i o u t 1 2 i o u t 1 1 i o u t 1 0 i o u t 9 i o u t 8 i o u t 7 i o u t 6 a g n d i g n d i g n d i g n d i g n d i g n d d v c c d g n d d a t a : d 0 t o d 9 f r o m d a t a b u s d v c c d g n d d v c c i g n d a g n d d g n d a v c c a d d r e s s b u s b u s c l k d a t a b u s 7 . 5 m h z 5 v 0 v 5 v 0 v 5 v 0 v v g , v r , v b : l e d d c s u p p l y v g = 5 . 5 v v r = 4 . 0 v v b = 5 . 5 v g g g g g g r e e n b b b b b f r o m x u p r f r o m x g f r o m x r f r o m i o u t 2 3 f r o m i o u t 1 r r r r r r e d b u l e f r o m x b f r o m i o u t 0 v p d upper/lower/rgb mode fig. 12. application circuit (2) application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility fo r any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same .
? 27 CXA2108AQ package outline unit: mm p a c k a g e s t r u c t u r e s o n y c o d e e i a j c o d e j e d e c c o d e q f p - 8 0 p - l 0 1 q f p 0 8 0 - p - 1 4 2 0 p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g 4 2 / c o p p e r a l l o y 1 . 6 g 2 3 . 9 0 . 4 2 0 . 0 0 . 1 + 0 . 4 1 8 0 6 5 6 4 4 1 4 0 2 5 2 4 0 . 8 0 . 3 5 0 . 1 + 0 . 1 5 1 4 . 0 0 . 1 + 0 . 4 1 7 . 9 0 . 4 1 6 . 3 0 . 1 0 . 0 5 + 0 . 2 2 . 7 5 0 . 1 5 + 0 . 3 5 0 . 8 0 . 2 0 . 1 5 0 . 0 5 + 0 . 1 8 0 p i n q f p ( p l a s t i c ) m 0 . 2 0 . 1 5 0 t o 1 0 d e t a i l a a

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